Hardware

An investigation into the behaviour of the Yamaha OPL3 chipset.
With a view to a more accurate emulator
sto
Posts: 60
Joined: Thu Nov 08, 2012 4:33 am

Re: Hardware

Post by sto »

So I guess this one should suffice? http://www.dx.com/p/logic-analyzer-w-du ... ack-148945

Looks like it is capable of generating the master clock signal rate.

And for putting it all together, I guess I need these, too:
opl3
Posts: 55
Joined: Sun Sep 26, 2010 8:11 pm

Re: Hardware

Post by opl3 »

I use very similar Cypress FX2-based logic analyzer.

To control the chip, I just put a sound card in a PC and write to IO port. But 8 channels in a logic analyzer is not enough to probe the OPL data bus, but if you want to track how it responds to certain write, you can at least have the write strobe and address bus bits in addition to audio output. And 24 MHz logic analyzer can't capture the 14.318MHz master clock of course.
sto
Posts: 60
Joined: Thu Nov 08, 2012 4:33 am

Re: Hardware

Post by sto »

Then I'll buy a teensy. Version 3.2 looks promising; it should be possible to map 72MHz down to about 14MHz without much pain.
opl3
Posts: 55
Joined: Sun Sep 26, 2010 8:11 pm

Re: Hardware

Post by opl3 »

OPL3 can work with 10-16MHz. I think in your case it does not matter what the master clock is.
sto
Posts: 60
Joined: Thu Nov 08, 2012 4:33 am

Re: Hardware

Post by sto »

I should receive all parts within two weeks :)
sto
Posts: 60
Joined: Thu Nov 08, 2012 4:33 am

Re: Hardware

Post by sto »

I received my teensy 3.1 a few hours ago, and already love it :D

But I'm a bit concerned about the required minimum master clock voltage of the OPL-3; the YMF262 specs say that the minimum is 3.5V, but the digital output pins only provide 3.3V. Should I connect the Vin power source through a digitally triggered transistor to the master clock input to raise the amplitude?
opl3
Posts: 55
Joined: Sun Sep 26, 2010 8:11 pm

Re: Hardware

Post by opl3 »

Stay away from discrete transistors, you most likely are not able to push 14 MHz signals through it.

One "proper" way to do logic level voltage translation is to use a buffer chip.
For example, a 74HCT125 is a buffer chip that can use 5V as supply (and output) voltage while accepting standard TTL level voltages on input (anything over 2V is high, anything below 0.8V is low). Anything in the HCT series are like that, basically you could use 74HCT04 inverter if you like.

Fortunately, only master clock and initial clear inputs are non-TTL compatible and need a buffer. The other pins can accept 3.3V levels.

But, you might have another problem: that the YMF262 output pins (e.g. data bus when reading) use 5V levels, so you should check if your Teensy has 5V tolerant IO pins, or only 3.3V tolerant.
sto
Posts: 60
Joined: Thu Nov 08, 2012 4:33 am

Re: Hardware

Post by sto »

As far as I'm understanding this, the 74HCT125 is basically a combination of 4 op-amps, right? Sounds indeed much more sane than a transistor, I remember a friend talking about the differences some years ago...

And yes, I have a teensy 3.1 with a 5V tolerance on the input pins. I will order a 74HCT125 and a second board, mine's too small for all this ;)
opl3
Posts: 55
Joined: Sun Sep 26, 2010 8:11 pm

Re: Hardware

Post by opl3 »

No, not op-amps, but digital buffer with input, output, and one control input to enable or disable (tri-state) the output.
So basically, it's overkill but so is everything else in 14-pin package :)
sto
Posts: 60
Joined: Thu Nov 08, 2012 4:33 am

Re: Hardware

Post by sto »

They just arrived, the last two they had in stock :)
It's a shame that the SMD adapters I ordered here in Germany on the same day haven't arrived yet.
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