FPGA implementation

An investigation into the behaviour of the Yamaha OPL3 chipset.
With a view to a more accurate emulator

Re: FPGA implementation

Postby carbon14 » Tue Nov 18, 2014 5:16 pm

I don't know if the Yamaha chips have a pipeline, in which the calculations actually take more than 8 cycles, but they overlap.

i.e. the first operator has been looked up, and envelope shaped and is now out of that part of the chip in time for the second operator to be envelope shaped, while the first operator is having tremolo added. (just by way of an example)

Code: Select all
Operator 1    Phase          Feedback       Waveform       Envelope       Tremolo        Accumulation
Operator 2                                  Phase          Feedback       Waveform       Envelope       Tremolo        Accumulation
Operator 3                                                                Phase          Feedback       Waveform       Envelope       Tremolo        Accumulation
Operator 4                                                                                              Phase          Modulation     Waveform       Envelope       Tremolo        Accumulation
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Re: FPGA implementation

Postby sto » Tue Nov 18, 2014 6:28 pm

Interesting... you got 12 steps there, which means there would be 2 clock cycles per step if you had 4 operator circuits. From my rare knowledge of digital circuits I'd say this perfectly matches one data fetch and one execution step if each one takes one clock cycle.
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Re: FPGA implementation

Postby carbon14 » Tue Nov 18, 2014 7:15 pm

This layout of steps was just off the top of my head, and I may have misled you somewhat. This was intended as an illustration of the opl2. With 2 operators per voice. I was referring to the fact that op1 modulates op4 and op2 modulates op5 etc. I have always wondered if this odd arrangement was to give scope to completely process op1 in time to affect the phase of op4.
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Re: FPGA implementation

Postby synthop » Tue Nov 18, 2014 8:48 pm

The way I architected my design, each operator slot is completely calculated by the end of it's time slot (7 cycles), and there is no overlap. The state machine processes them in order, so lower numbered operator slots are processed first (which as you mentioned is convenient for the modulation scheme).

Within each operator slot, all functions are done in parallel, though there is some pipelining within functions (ROM lookups are registered, multipliers are registered, I had also registered adders but the clock period is so long its really not necessary). Some functions are data dependent on others (the envelope affects the exponential ROM input), but these all flow through and stabilize by the end of the time slot.
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Re: FPGA implementation

Postby synthop » Wed Nov 19, 2014 3:00 am

But please do let me know if you think this doesn't sound right.
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Re: FPGA implementation

Postby opl3 » Wed Nov 19, 2014 12:30 pm

Hello,

sorry I am late to the party, but I have been busy with real life, although have been reading the forum.

First of all, hi Synthop and I am impressed with your progress, I hope I can be of assistance.

I have very little prior FPGA knowledge, but I have been looking for a way to jump in to FPGA developement (just because I also want OPL emulation in FPGA) and I am willing to learn and this would be a good starting point.

I will be getting a FPGA board, do you recommend I also get the ZYBO Zynq board or something else? Is the FPGA part big enough for something else than OPL3 as well? I have been thinking about FPGA ISA card for retro stuff, such as sound card or video card emulation.
If there would be a similar board with Altera chip, it would be even better (could convince people at work to get this for me).
It could be easiest if I just get the same ZYNC board, so there is less "porting" of the code to another chip or whatever it takes.

Do you have a repository for the OPL3 FPGA project online somewhere? I'd be happy to test your code when I get the ZYBO board. If I have problems getting started with ZYBO, can I ask you for some guidance?

For the operator calculation order, please take a look at Y-8950 application manual page 11 (13 in pdf) for OPL2 calculation order (op1,op2,op3,op4,op5,op6...), I have not figured out how that would be extended to OPL3 however.
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Re: FPGA implementation

Postby synthop » Wed Nov 19, 2014 2:04 pm

Hi opl3, yeah I think this would be a great project to learn some FPGA coding, especially because you obviously already have an interest in the OPL3.

I chose the Zybo for a couple main reasons:
  • I wanted to play around with those dual ARM cores, their interaction with the programmable logic, and dig into low level Linux kernel and driver development
  • It along with the Microzed are the two most inexpensive Zynq boards, but the Zybo has the audio codec/DAC and PMOD connectors

It's a very nice board. I think the FPGA is plenty big enough for a beginner board, but it is the smallest of the Zynq series. Once I got my head out of the fog I realized the Zybo will easily fit the OPL3 with plenty of room to spare--I estimate utilization will end up around 40%. But that is a major portion of the chip. If you have the money for it, you might want to upgrade to the Zedboard which as I mentioned earlier in the thread has a much larger FPGA. The codec chip is different, but they both use an i2s data interface. I do the i2c configuration for the chip using software in the ARM--you'd probably do something similar on the Zedboard.

Altera has some similar boards. I just did a quick google search and found this: http://www.terasic.com.tw/cgi-bin/page/ ... ish&No=836

You could port this design easily to an Altera chip as all the OPL3 stuff is done in straight RTL, nothing vendor specific. I do use a Xilinx-specific PLL to generate the 12.727MHz clock down from the 125MHz input clock--I'm sure there's an Altera equivalent.

I will help you as much as I can. I'm also trying to get a couple people at work into FPGA design as well (I work with all software people at my current job). First thing I told them was if you can figure out the damn tool chain and environment, you're halfway there. Haha. Not exactly, but the toolchains for FPGAs are pretty huge pains in the ass.

EDIT: If you do get the Altera board, the interface to the ARM core will be different. That might be a hurdle. The Zybo is definitely the easiest path.
Last edited by synthop on Thu Nov 20, 2014 6:05 am, edited 2 times in total.
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Re: FPGA implementation

Postby synthop » Wed Nov 19, 2014 2:09 pm

As far as a code repository, I'm just using my own personal SVN repo at the moment. But if you do decide to get in on this, I can put it up on like Github or something like that. I kind of planned on doing that eventually anyway.
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Re: FPGA implementation

Postby opl3 » Tue Nov 25, 2014 9:59 am

Alright, the ZYBO is now ordered, don't know how long it will take to arrive.
Most likely it will take some time for me to set up the developement environment and go through the available example projects first.

I would really appreciate it if you put the project to Github or wherever when you have the time so I can test this.
I don't have a Github account, but I am familiar with BitBucket.

Did you solve the operator order problem you had?
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Re: FPGA implementation

Postby synthop » Wed Nov 26, 2014 9:22 pm

Awesome! I'll try to get the project up online next week. This week is pretty hectic with the Thanksgiving holiday over here in the US.

I don't think I have an operator order problem at the moment. The operators are calculated in order (1-36), which should work as lower-ordered operators always modulate higher-ordered operators, unless I'm understanding it incorrectly.
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