https://www.dropbox.com/s/2pq17ls94qswfcl/BOOT.bin?dl=0
As far as building from scratch, I have scripts setup to build the FPGA but not the software portion and boot image yet. In the FPGA folder, you may simply run 'make bitstream' to build an FPGA image that may be loaded onto the SD card or loaded in via JTAG (which is normally how I do it for debugging). This is assuming you're under a Linux environment, with Xilinx Vivado 2015.1 installed and in your path. I'll soon get around to creating scripts for the software portion and boot image.
I've since discovered that the feedback seems to be causing some fuzzy sounding distortion apparent during certain songs (it goes away if I set feedback to 0). I'm trying to figure out why Steffen is shifting the feedback by 9 in his code:
- Code: Select all
/**
* @brief Calculate adjusted phase feedback
* @return Adjusted phase feedback using m_fb (11 bit)
*
* @details
* The OPL stores the last 2 samples independent of feedback.
*/
int16_t feedback() const {
if( m_fb == 0 ) {
return 0;
}
return ( ( m_feedback[0] + m_feedback[1] ) << m_fb ) >> 9;
}
/**
* @brief Push feedback into the queue
* @param[in] fb 13 bit feedback from channel output
*/
void pushFeedback( int16_t fb ) {
m_feedback[0] = m_feedback[1];
m_feedback[1] = fb;
}
I'm replicating this exact code in the FPGA. I may also have an issue with assigning the values at the wrong time in the time slot; I need to check this more thoroughly in simulation.