FPGA implementation

An investigation into the behaviour of the Yamaha OPL3 chipset.
With a view to a more accurate emulator

Re: FPGA implementation

Postby synthop » Fri Dec 12, 2014 9:45 pm

Probably the best way to delve in is to check out the original datasheet from Yahama: http://web.archive.org/web/20030520163334/http://www.fit.vutbr.cz/~arnost/opl/lost+found/ymf262.pdf
synthop
 
Posts: 33
Joined: Sun Oct 26, 2014 9:21 pm
Location: Brooklyn, New York, USA

Re: FPGA implementation

Postby Dongulus » Thu Dec 18, 2014 8:37 pm

Since you are using a Zynq, which contains the ARM A9 core, are you planning on building the CPU interface as it is described in the datasheet, or will you just have the A9 access those registers directly through the AXI interconnect?
Dongulus
 
Posts: 2
Joined: Mon Dec 08, 2014 7:07 pm
Location: San Diego, California

Re: FPGA implementation

Postby synthop » Thu Dec 18, 2014 9:20 pm

I'm going to go through an AXI4-Lite interface to the ARM. The DAC interface is also different, as well as the clock speed from the original chip. This is all to match the external interfaces on this particular board. The design should be easy to mod to replicate the exact chip interfaces.

I'm at the point where I need to test the register interface, I just haven't had time to do it. The next step is to port software to the ARM that can write to the device and play music (I'd like to start with stuff that doesn't use the rhythm mode and then add that later).
synthop
 
Posts: 33
Joined: Sun Oct 26, 2014 9:21 pm
Location: Brooklyn, New York, USA

Re: FPGA implementation

Postby synthop » Wed Jan 07, 2015 9:02 pm

I have a question for you software guys. What do you think is the easiest path to getting software up on the CPU to play some tunes and test the FPGA? The OPL3 is memory mapped in the ARM. I'd prefer something bare-metal at first for simplicity, but there are a couple versions of Linux I can put on it. Should I port an existing midi player? I'm open to suggestions.
synthop
 
Posts: 33
Joined: Sun Oct 26, 2014 9:21 pm
Location: Brooklyn, New York, USA

Re: FPGA implementation

Postby opl3 » Wed Jan 07, 2015 11:05 pm

Well I would suggest starting from the easier file formats that are basically register dumps with timestamps. Apogee .IMF format, .VGM format and DosBox .DRO format for example. There should be plenty of example tunes in each of these formats at VGMPF wiki.

DRO format has timebase of 1 millisecond (1000Hz timer ticks), and there are a few .IMF versions (Wolf3D is about 700Hz timebase), and .VGM format is based on 44100Hz timebase (common audio sampling rate).

So if you are able to generate a 1000Hz or 700Hz timer or just a simple delay of 1ms, you should have results soon.

Playing anything MIDI-like is far more complex and most likely ends up not sounding like original music in games for example unless you reverse engineer the playing routine how the MIDI data is processed to OPL chip writes so you end up with basically register writes and time delays like in the original game.
opl3
 
Posts: 55
Joined: Sun Sep 26, 2010 8:11 pm

Re: FPGA implementation

Postby synthop » Thu Jan 08, 2015 4:59 pm

Register dumps with timestamps sounds perfectly simple. Thanks for the heads up. With those two timers in the OPL3 I can easily generate the delays (I might even just NOP loop at first).
synthop
 
Posts: 33
Joined: Sun Oct 26, 2014 9:21 pm
Location: Brooklyn, New York, USA

Re: FPGA implementation

Postby synthop » Thu Jul 09, 2015 5:18 am

First and foremost, I have music playing!

Sorry I've been out of the loop for a few months. I was traveling and also moved so I had to take a step back for a while. I recently just started back up with the project and have made some good progress in the last few days.

I ported imfplay since it seemed very simple:
http://software.kvee.cz/imfplay/

It was pretty easy to port over to the ARM. I'm running bare metal and using an in-memory filesystem to store my DRO file. I wanted to keep it as simple as possible at first.

After fixing a bug in how the channels were combined I was beyond excited to hear music! I have something resembling the music I'm expecting, but it's definitely off a bit in terms of tone and timbre. Some instruments seem very close, while others are very off. I suspect I'm either making a mistake in my math or something is getting corrupted.

Soon I'll post some recordings of the output along with the DRO files I'm using.
synthop
 
Posts: 33
Joined: Sun Oct 26, 2014 9:21 pm
Location: Brooklyn, New York, USA

Re: FPGA implementation

Postby synthop » Sun Jul 12, 2015 5:58 pm

I've gotten much much closer. The sound is similar to DOSBox but sounds less buzzy?

I changed my phase increment calculation to use signed arithmetic and also I was adding the modulation into the phase accumulator instead of just the output.

At this point it sounds pretty good I think, even without the rhythm instruments implemented.

Check out a couple doom songs:
https://www.dropbox.com/s/ushpil4lqat8c ... 0.mp3?dl=0
https://www.dropbox.com/s/yf7d6uh1ed3r0 ... 1.mp3?dl=0

And a youtube video:
https://www.youtube.com/watch?v=pkNNPkmWzAQ

Sorry for the shitty noisy recording. The ZYBO only has a headphone output, not a true line out...although the DAC does so I may hay wire it.

Next step is to implement the rhythm instruments and narrow down why it sounds slightly different than DOSBox.
synthop
 
Posts: 33
Joined: Sun Oct 26, 2014 9:21 pm
Location: Brooklyn, New York, USA

Re: FPGA implementation

Postby synthop » Mon Jul 13, 2015 11:20 pm

Ah I think I'm very close! I can't tell the difference between DosBOX and the FPGA now.

I was shifting the modulation value by the wrong amount when adding it to the phase. I also had to use an arithmetic shift for the feedback value (SystemVerilog has separate logical and arithmetic operators).

Here's the first doom song again. It sounds much better:
https://www.dropbox.com/s/xx1zdo1oi5bug ... 2.mp3?dl=0

I still need to do more testing to verify everything is correct. One thing is imfplay doesn't use the second bank of registers, so that's a thing. I probably need much better test cases too to get full coverage.
synthop
 
Posts: 33
Joined: Sun Oct 26, 2014 9:21 pm
Location: Brooklyn, New York, USA

Re: FPGA implementation

Postby opl3 » Tue Jul 14, 2015 6:41 pm

Nice! I would like to try that too if you have the SD card image somewhere handy. Is there also a readme if I want to rebuild it (I still don't know where to start)?

Yes, IMF format supports OPL2, or first bank only. DRO files do support OPL3, as well as VGM ver 1.51+ files. I have some preliminary OPL2 VGM player for DOS, but it is written in Turbo Pascal. I might rewrite it in C sometime.

Edit: On a side note, I have tried to see what the reserved test register does, and it seems at least 3 bits alter the sound somehow. I'll start a new topic about this when I have any more info.
opl3
 
Posts: 55
Joined: Sun Sep 26, 2010 8:11 pm

PreviousNext

Return to Yamaha OPL-3 research

Who is online

Users browsing this forum: No registered users and 1 guest

cron