Other research

An investigation into the behaviour of the Yamaha OPL3 chipset.
With a view to a more accurate emulator

Other research

Postby carbon14 » Thu Jun 30, 2011 3:04 pm

I've been looking at the application manual for the Y8950, the MSX audio chip produced by Yamaha for cross manufacturer MSX computers produced in the 80s.

On page 11, it states "The MSX-AUDIO can generate nine different FM sounds (nine channels). It has a single operator cell, but the operator cell is sequentially used 18 times to calculate and generate the nine different sounds."

In other words, the 'operator cell' which does the bulk of the processing is not duplicated 18 times within the device, but used 18 times during each sample cycle.




On page 4 there is a block diagram of a single operator using feedback. The accompanying equation to describe the feedback synthesis is:

F(t) = A SIN (ωt + ΒF(t))

where ω is the input to the phase generator and Β is the depth of feedback.

What's interesting to note is the claim in the equation that the value of F (the output) for a given value t is dependant on the value F for that same value t. This cannot be literally correct, such a recursive equation my have no solutions. I suspect that that in truth the value is dependant either on the value of F for t-1, or on some first approximation to F of t.
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Re: Other research

Postby carbon14 » Thu Jun 30, 2011 3:12 pm

Page 29 gives a good description of the accumulator.
The data from the operator cell is a floating point value, with a 10 bit virtual part (including sign bits) and a 3 bit exponent. The accumulator is also floating point. Data is then converted to a slightly different form for the 13-bit output format as used in the OPL2.

It seems likely therefore that the OPL2 does indeed have a floating point accumulator also.
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Re: Other research

Postby opl3 » Sun Jul 03, 2011 8:37 pm

carbon14 wrote:Page 29 gives a good description of the accumulator.
The data from the operator cell is a floating point value, with a 10 bit virtual part (including sign bits) and a 3 bit exponent. The accumulator is also floating point. Data is then converted to a slightly different form for the 13-bit output format as used in the OPL2.

It seems likely therefore that the OPL2 does indeed have a floating point accumulator also.


But to me that text on page 29 and picture on page 30 tells me the exact opposite, the accumulator being linear (PCM), not float.

In the text, it says "The accumulator collects operator output for each channel and converts the accumulated result into offset binary data with 10-bit virtual part and a 3-bit exponent part". So it does not say in what format the value is internally in accumulator, just that it is converted to float before output.

In the picture, it shows how the internal OPL data (it looks definitely being 16-bit offset binary number) in accumulator is converted to float for output. The least significant bits are ignored and only most significant bits are used for output, and the leading unsignificant bits are used to count the shift value. This is exactly the same in reverse how Olli's code reconstructs the 16-bit PCM value out of the float output from the chip.

I have also been thinking for the past few days reasons why the accumulator would be in float or in linear (PCM), and came into following conclusions just to back my hypothesis.

The operator output from sine lookup has to be always converted from float to linear (PCM) because the output can be fed to three different things that makes sense to be linear: modulator output feeds carrier input linearly, feedback is used to feed operator output back to operator input linearly, and of course a carrier output is fed to accumulator.

It is also much easier to make the accumulator hardware to just sum linear (PCM) values together (like phase accumulator), instead of summing two float values together. At least if operator output already needs to be linear (PCM) because it can be used for other things as well.

However I do understand it is not that hard to perform sum of two floats either, and there will be rounding errors if only 9 bits + sign bit is used for mantissa and 3 bits for exponent. The internal format seems to have 15 bits + sign bit anyway to avoid rounding errors.
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Re: Other research

Postby carbon14 » Mon Jul 04, 2011 8:03 am

I think those are good arguments, I am persuaded.

As I have said elsewhere, it should be possible to test one way or the other. By accumulating small and large amplitude signals one should be able to force rounding errors into a floating point accumulator, which would not appear in a full width accumulator. I don't have an OPL2 to play with, so for the time being this experiment is moot, but I am now inclined to your opinion here.
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