Page 1 of 1

Interrupt Pin

PostPosted: Fri Nov 23, 2012 2:04 pm
by carbon14
It's been over a month since I did anything with this, but today I got some experiments done.

Loading a value into the timer and letting the timer run, eventually the IRQ is pulled low. This happens on the 17th clock cycle of a 72-clock data frame. But which frame.

The timer 1 has a period of 80μs which is once every 4 frames (or samples).

My protocol was to reset the chip (pull IC low for at least 80 cycles, then load the data into the timer and finally start the timer. By choosing which clock cycle during the frame I loaded the start timer instruction, I hoped to pin down some facts about what goes on in the chip. I've not yet fully analysed that data.

For each possible starting point that I was testing, I ran the above process 100 times, i.e. reset the chip, load the timer, start the timer on a specific clock pulse, monitor the IRQ and record when it is pulled low, then repeat.

Typically the results were that the line was pulled low in any one of 4 different frames, but these 4 possible frames occurred one after another in a repeating pattern within my results set. This is consistent with the interrupt timer having an internal counter with the same period as the main sampling frequency of the chip. Effectively a two bit counter clocking on every frame, and when it turns over it increments the timer value.

This is interesting because it suggests that a chip reset (IC) does not reset this 2 bit counter, but it does reset the point at which the 2 bit counter itself is clocked. I suspect that the 2-bit counter is clocked at the start of a nominal 16-bit data frame, i.e. after the first two bits of spurious data are output. In the OPL-2 chip this is followed by 3 more spurious bits, and then the start of the 10.3 floating point data.

If the same architecture is used in the OPL-3 then then 2-bit clock occurs at the start of the 16-bit output data (the OPL-3 output is not floating point encoded)

The fact that all 4 possible interrupt frames occur in my output is explained by the fact that the total number of frames in one run of the experiment is not a multiple of 4.

If I change the frame starting point, I am at some point changing the total number of frames (and part frames) in my experiment, and the output frames change to a cycle of just two values.

I should be able to build a more comprehensive model of this process when I've had a chance to analyse all the data more fully.

I predict that timer 2 can be made to output a cycle of 16 different output points, because it's period is a further 4 times longer than that of timer 1

Re: Interrupt Pin

PostPosted: Sat Nov 24, 2012 10:29 am
by carbon14
Timer 2 does indeed trip the interrupt line at the same consistent point in the frame, but that frame is one of 16 frames within the 320μs period of the timer. From my experiments, the timings are consistent with there being a single 4 bit counter, with the lower 2 bits being shared with timer 1. These experiments are not conclusive, it's the kind of thing which would be easy to disprove and hard to prove, but for now I'm relying on Occam's razor.