An investigation into the timing of a Yamaha YM3812 (OPL-2) chip


Postby carbon14 » Tue Sep 11, 2012 8:13 am

There is a hardware reset on the OPL chips. On the YM3812 pin IC is normally pulled high internally. If you pull it low it resets all the registers in the chip.

I wanted to know the effect of a reset on the timing signals. It resets them. Simple.

The ΦSY rises on the 4th rising edge of ΦM following the pull down of IC. At this point the value of MO could be regarded as bit X2.
On the 66th rising edge of ΦM following the pulldown if IC, ΦSH falls, which signals the boundary between data frames, so a full 16 bits of data are delivered via MO during this period.
All of that data should be regarded as suspect, it's presumably the latched content of the output serializer prior to the reset.

The minimum width for the reset pulse is 80 cycles of ΦM, so IC should not be allowed to rise for at least a further 14 cycles, and during this time MO will output bits X0-X3 which are junk anyway.

The first valid 13-bit value can be read from the chip from cycle 86 onwards, and the ΦSH signal which marks the end of that 13-bit value occurs on the 138th rising edge of ΦM after IC was pulled low.

The end of the reset pulse seems at first glance to have no bearing on the behaviour. Other than the stated requirement that it's minimum width is 80 cycles, I believe that the chip is usable irrespective of the state of IC.

All of this may seem a little esoteric for research, but having a solid prediction for the data boundaries following a reset, obviates the need to read ΦSY and ΦSH. Instead, ΦM cycles can be counted following the start of the reset, and MO can be read at appropriate points avoiding the overhead of reading the additional timing signals. This frees up a great deal of processing time to write registers while maintaining the necessary clock rates.

I should say that my initial runs, with a deliberately slow process that was writing to the screen during processing produced inconsistent data output from the chip, while the faster code which buffered the output data in memory seems to produce consistent output from the chip, suggesting that the minimum clock speeds have a genuine impact on the chip behaviour.
User avatar
Posts: 124
Joined: Tue Aug 05, 2008 9:11 am
Location: York, England

Return to Yamaha OPL-2 research

Who is online

Users browsing this forum: No registered users and 1 guest