Timing Control

An investigation into the timing of a Yamaha YM3812 (OPL-2) chip

Timing Control

Postby carbon14 » Mon Aug 20, 2012 11:06 am

Using the Raspberry-pi I've been examining the timing control for the YM3812.

The input clock (ΦM) is a square wave, ideally between 2 and 4MHz. From this are derived output clocks (ΦSY and ΦSH) which synchronise the digital output datastream (MO).

The Nominal frequency for ΦM, (fM) is 3.57MHz
and the corresponding sample rate for the output fSH is just below 50KHz.

So fM = 72 × fSH

The datasheet for the YM3812 is not particularly clear on the timings for ΦSY, ΦSH and MO, but these outputs are the inputs to the Yamaha YM3014B DAC chip.

The YM3014B datasheet shows a timing diagram which depicts 16 bits of data in each sample. The first 3 are redundant and should be ignored, the next 10 are the mantissa and the remaining 3 are the exponent.

To get 16 bits of data out during 72 cycles of ΦM would suggest that fM = 4.5 × fSY. This would be a little odd but not completely unfeasible.

In fact, contrary to the diagram in the YM3014B datasheet, there are 18 bits of data delivered for each sample, the first 5 of which are redundant. I will label these 18 bits as:
X0 X1 X2 X3 X4 X5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 S0 S1 S2

So fM = 4 × fSY.

The data on MO changes on a rising edge of ΦM and persists for 4 cycles of ΦM.
ΦSY rises on the rising edge of ΦM, 25% through the 4 cycles of ΦM and falls on the following rising edge of ΦM. It has a duty cycle of 25%
ΦSH has a duty cycle of 32 / 72, rising as MO changes to the 11th bit (D4) and falling at the end of the sample (after S2)

YM3812timing.png
timing diagram
YM3812timing.png (7.15 KiB) Viewed 2648 times


So the easiest way to read the data is to detect the falling edge of ΦSY and read the value of MO into an 18* bit serial to parallel shift register. When ΦSH falls the parallel output should be latched for processing.

* because the first 5 bits are to be ignored, you would probably use a 16-bit shift register and just let the first two bits fall out of the end.
User avatar
carbon14
 
Posts: 124
Joined: Tue Aug 05, 2008 9:11 am
Location: York, England

Re: Timing Control

Postby opl3 » Tue Aug 21, 2012 9:51 am

I confirm the signal outputs. I can even post some real logic analyzer pictures if I can still find them. What is interesting that either rising or falling edge of bit clock (SY) can be used to clock data and latch signal (SH) in.

The YM3014B DAC will load data in at rising bit clock (SY), and of course falling edge of latch (SH) signal. It seems that the latch signal needs to be stable before bit clock edge so it is not asynchronous latch, but synchronous to the bit clock. The datasheet also mentions it will happily work with more or less than only 16 data bits per sample, by increasing or decreasing the amount of non-used bits. So 18 bits is OK.

The output will be interesting, because you always have 10 bits of value and 7 levels of magnitude (one code out of the 3-bit value is invalid), meaning it has 10-bit resolution but 16-bit range. Low amplitude values still use full 10-bits, so at some point I thought it could be possible to have more LSBs out from OPL-2 than from OPL-3, because OPL-3 is fixed to 16-bit resolution and range, and the operator output is more than 10 bits with more than 7 levels of magnitude. But I assume the relative amplitudes match so it is not possible. I have already some OPL-2 music captures and converted to PCM for playback or MP3 conversion, but I have not analyzed the output. In theory an emulator could output more than 10-bit or 16-bit range, but it would not match the original then, just a nice option to have 24 or 32 PCM audio output.

I do not know about the minimum master clock frequency. It may be specified because of two reasons. Smaller frequency would either not yield usable output note range, usable output sampling rate, or the chip just uses dynamic logic gates internally which cannot store charge for longer periods so minimum operating frequency is required.
opl3
 
Posts: 55
Joined: Sun Sep 26, 2010 8:11 pm

Re: Timing Control

Postby carbon14 » Tue Aug 21, 2012 1:20 pm

I believe that the output range is the same for both the OPL-2 and the OPL-3. The OPL-2 outputs either bits 0-9 of a 16-bit value, or bits 6-15 of a 16-bit value, or 10 bits in between.
These 16-bit values correspond to those of the OPL-3.

The OPL-3 however can maintain the subtleties of a very low amplitude oscilator whilst simultaneously outputting very large amplitudes.
These subtleties are probably lost on the human ear, and they are discarded by Yamaha's recommended DAC, which although it takes in a 16-bit value, is still internally a 10 level DAC with a 7 stage shift.


Your last paragraph on the minimum clock speed is what I was thinking. 50kHz sampling rate is generally regarded as the top end of human fidelity. I believe that CDs are around 48kHz. But charge based devices within the chip would pose a problem. The registers themselves seem the most likely candidates for that.

I think that I can generate a clock at over 4MHz using the raspberry-pi. Which means that I can afford to do a little bit more work and perhaps still creep in within the 2MHz limit. It takes around 22 signal changes to write a register, but I can spread that out 1 change at a time between clock pulses, and still get 6 register changes in per sample (considerably faster than my DOS pc currently acheives in my OPL-3 setup). Since I want to be able to read the output as well, I could write register changes after rising clock edges, and read either SY, MO or SH after falling clock edges and still be close to the speed limit, with time to write 3 register changes per sample.
User avatar
carbon14
 
Posts: 124
Joined: Tue Aug 05, 2008 9:11 am
Location: York, England


Return to Yamaha OPL-2 research

Who is online

Users browsing this forum: No registered users and 1 guest

cron