Search found 2 matches
- Thu Dec 18, 2014 8:37 pm
- Forum: Yamaha OPL-3 research
- Topic: FPGA implementation
- Replies: 54
- Views: 846499
Re: FPGA implementation
Since you are using a Zynq, which contains the ARM A9 core, are you planning on building the CPU interface as it is described in the datasheet, or will you just have the A9 access those registers directly through the AXI interconnect?
- Thu Dec 11, 2014 7:32 pm
- Forum: Yamaha OPL-3 research
- Topic: FPGA implementation
- Replies: 54
- Views: 846499
Re: FPGA implementation
Hello synthop,
I've successfully followed you here from your Reddit post and so far I've only just glanced over your GitHub. Coming from a PL background and only a basic knowledge of audio synthesizers, I'm trying to get an understanding of the system level overview and features for the OPL-3. Could ...
I've successfully followed you here from your Reddit post and so far I've only just glanced over your GitHub. Coming from a PL background and only a basic knowledge of audio synthesizers, I'm trying to get an understanding of the system level overview and features for the OPL-3. Could ...