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Visibility is great isn't is? Glad you crossed that off the list. Keep us updated.

Do you have a scope? First thing I do when I bring up a new board or whatever is check the clocks, resets, power, ground. I know it sounds overly basic but often times one of those is the problem.

Okay that makes sense, sort of. If Descent is not using rhythm mode, wouldn't the dropouts occur on any channel really? I think I may have noticed this occurring on other songs, but I'm not totally sure due to my lack of having original hardware. Also there are other sources of error such as the ...

That means a lot man, thanks. Honestly I would not have gotten very far without all the time and effort you all put into reverse engineering this chip. Amazing work.

Xilinx seemed to think this was pretty cool:
https://twitter.com/XilinxInc/status/628274638909390848
http://forums.xilinx.com/t5/Xcell-Daily ... a-p/644910

So I've implemented the rhythm instruments. It's hard to tell if they're working or not because I'm not sure if the music I'm listening to is using them or not. If you guys have some tough test cases (preferably in DRO format) I'd like to push it through.

Here's another youtube video, this one ...

Okay I think we just had a little bit of a mix up on semantics, but that was not the problem anyway. I was in fact latching the feedback in the wrong operator time slot, and the value was also being truncated. I fixed both problems and things sound very good now with feedback.

Next onto the rhythm ...

Glad it works for you! Yeah the debug output on the console doesn't do much right now except list the files in the In-Memory Filesystem. The software is so minimal; I just hacked it up to test the FPGA--it's hardcoded to play one song. I'd like to have a command line interface to play songs and/or ...

Here's an SD card image:
https://www.dropbox.com/s/2pq17ls94qswfcl/BOOT.bin?dl=0

As far as building from scratch, I have scripts setup to build the FPGA but not the software portion and boot image yet. In the FPGA folder, you may simply run 'make bitstream' to build an FPGA image that may be loaded ...

Ah I think I'm very close! I can't tell the difference between DosBOX and the FPGA now.

I was shifting the modulation value by the wrong amount when adding it to the phase. I also had to use an arithmetic shift for the feedback value (SystemVerilog has separate logical and arithmetic operators ...