Search found 55 matches
- Mon Jan 18, 2016 8:24 pm
- Forum: Yamaha OPL-3 research
- Topic: Hardware
- Replies: 30
- Views: 587789
Re: Hardware
I bet the yellow is your 12MHz masterclock (M) from Teensy, and blue is 1.5 MHz bitclock (SY) from YMF262 because it has 25% duty cycle.
- Fri Oct 30, 2015 9:12 pm
- Forum: Yamaha OPL-3 research
- Topic: Hardware
- Replies: 30
- Views: 587789
Re: Hardware
Hi, I don't know how this Teensy environment works, but my guess is the serial port writes are not buffered, so at 9600 bps, each byte sent to serial port takes about 1.04 milliseconds to transfer, and the SY polling must be done at twice the SY frequency, ~3.6MHz. There's no time for sending serial ...
- Wed Oct 07, 2015 6:49 pm
- Forum: Yamaha OPL-3 research
- Topic: Hardware
- Replies: 30
- Views: 587789
Re: Hardware
No, not op-amps, but digital buffer with input, output, and one control input to enable or disable (tri-state) the output.
So basically, it's overkill but so is everything else in 14-pin package
So basically, it's overkill but so is everything else in 14-pin package
- Tue Oct 06, 2015 9:17 pm
- Forum: Yamaha OPL-3 research
- Topic: Hardware
- Replies: 30
- Views: 587789
Re: Hardware
Stay away from discrete transistors, you most likely are not able to push 14 MHz signals through it.
One "proper" way to do logic level voltage translation is to use a buffer chip.
For example, a 74HCT125 is a buffer chip that can use 5V as supply (and output) voltage while accepting standard TTL ...
One "proper" way to do logic level voltage translation is to use a buffer chip.
For example, a 74HCT125 is a buffer chip that can use 5V as supply (and output) voltage while accepting standard TTL ...
- Fri Oct 02, 2015 5:52 pm
- Forum: Yamaha OPL-3 research
- Topic: Hardware
- Replies: 30
- Views: 587789
Re: Hardware
OPL3 can work with 10-16MHz. I think in your case it does not matter what the master clock is.
- Fri Oct 02, 2015 5:03 pm
- Forum: Yamaha OPL-3 research
- Topic: Hardware
- Replies: 30
- Views: 587789
Re: Hardware
I use very similar Cypress FX2-based logic analyzer.
To control the chip, I just put a sound card in a PC and write to IO port. But 8 channels in a logic analyzer is not enough to probe the OPL data bus, but if you want to track how it responds to certain write, you can at least have the write ...
To control the chip, I just put a sound card in a PC and write to IO port. But 8 channels in a logic analyzer is not enough to probe the OPL data bus, but if you want to track how it responds to certain write, you can at least have the write ...
- Thu Oct 01, 2015 6:17 pm
- Forum: Yamaha OPL-3 research
- Topic: Hardware
- Replies: 30
- Views: 587789
Re: Hardware
My suggestion is to get a USB logic analyzer, one that can capture as long as PC memory runs out.
For OPL3, you need at least 8MHz sampling rate to capture the serial audio stream.
For OPL3, you need at least 8MHz sampling rate to capture the serial audio stream.
- Thu Jul 30, 2015 10:33 pm
- Forum: Yamaha OPL-3 research
- Topic: FPGA implementation
- Replies: 54
- Views: 851123
Re: FPGA implementation
I tried the latest binary, it sounds very nice although I don't remember the original song (I have heard Descent..)
I have very little knowledge which songs use rhythm but the ones I have don't use it.
Try to search VGMPF for songs, but they may not have many in .DRO format. I have a crude .vgm ...
I have very little knowledge which songs use rhythm but the ones I have don't use it.
Try to search VGMPF for songs, but they may not have many in .DRO format. I have a crude .vgm ...
- Fri Jul 17, 2015 8:55 am
- Forum: Yamaha OPL-3 research
- Topic: FPGA implementation
- Replies: 54
- Views: 851123
Re: FPGA implementation
I also recall there are some DosBox/ScummVM versions with OPL passthrough if you happen to have a sound card with onboard OPL. So yes, interesting. It's enough to emulate the OPL3, I would not want to write a full 386 emulation for FPGA :) Maybe anything below 286 is easy enough though..
Anyway ...
Anyway ...
- Wed Jul 15, 2015 8:31 pm
- Forum: Yamaha OPL-3 research
- Topic: FPGA implementation
- Replies: 54
- Views: 851123
Re: FPGA implementation
Thanks, the image works and plays Doom music. I see the terminal has some debug output at 115200 bps, listing some songs, but can I control it somehow?
About the feedback,
The m_fb variable holds 0..7 just like FB bits in register of real chip.
When m_fb is 0, there is no feedback.
Steffen's phase ...
About the feedback,
The m_fb variable holds 0..7 just like FB bits in register of real chip.
When m_fb is 0, there is no feedback.
Steffen's phase ...